In previous experiments, it has been possible to make integrated circuits and other electronic devices based on GaAs and InP. Such devices are made on single crystalline semiconductors where electric current does not flow, also is known as semi-insulators. Electric conductivity at room temperature in these materials is due to free charge carriers which are introduced by impurities, that is, atoms of some chemical elements other than those constituting the matrix of the semiconductor. For example, in regard to GaAs, impurities are atoms of chemical elements which are neither Ga nor As. The materials by their electronic structure and location in the crystal, introduce free charge carriers at room temperatures as electrons or holes. In the case of GaAs and InP bulk single crystalline materials, in spite of the care taken during the preparation and growth to avoid incorporation of impurities, they have a high concentration of impurities which make these crystals conductive. Nevertheless, since the manufacture of integrated circuits and some electronic devices are based on semi-insulating single crystalline substrates for the physical and chemical processes needed in their manufacture, procedures have been developed to make these semi-insulating crystals. The processes most often used for this purpose are: i) controlled incorporation of impurities, which introduces energy levels close to the middle of the energy forbidden band gap of the semiconductor of interest. When such impurities are added in the proper quantity and type, they compensate for the impurities which give the free charge carriers by reducing the electrical conductivity of the crystal. An example of this process is the addition of chromium (Cr) to Gallium arsenide and Fe to Indium phosphide. ii) The second possibility, which is commonly used in GaAs, consists of growing the crystal with a low acceptor impurity concentration from a melt lightly out of stoichiometry. For example, an impurity which is arsenic rich, under conditions such that the deep donor level, EL2, is formed in the crystal in concentrations higher than those of the shallow acceptors. By such a process the Fermi level is pinned around the middle of the energy band gap and the crystal becomes semi-insulating. In spite of the effort developed in this direction, the use of crystals obtained by this technology is strongly limited because of their poor quality since they usually have a high density of crystalographic defects, dislocation networks, undesired residual impurities and above all these defects are distributed highly nonhomogeneously in the bulk of the crystal. The effects of such imperfections and their nonhomogeneous distribution through the crystal on the properties of the integrated circuits and other electronic devices made on them, are all negative. Among the most frequent undesired effects are: fluctuations in the threshold voltage of field effect transistor from point to point on the wafer and even on a single integrated circuit, reduction of the power gain, increase of the electric noise on the transistors and, the worst of all, the drastic reduction of the production yield limiting the development of this material.
An attempted solution to this problem consists of growing on the above described crystal an epitaxial buffer layer having fewer defects than the substrate. This can be done using any of the well know epitaxial techniques, such as: Liquid Phase Epitaxy, Chemical Vapor Deposition; OM-CVD, molecular beam epitaxy (MBE) or any mixed technique. Layers obtained by any of these techniques are very homogeneous in their physical properties, have good surface morphology such as a mirror smooth surface to make the photolithographic processes necessary to the manufacture of integrated circuits and other electronic devices.
The high resistivity or semi-insulating behavior in these layers is achieved using one of the two options described below: a) adding in a controlled way impurities which reduce the free charge carriers concentration exactly as in case (i) describe before for the bulk materials, and b) growing very high purity epilayers having high resistivity, although usually lower than the one obtained by process (a). The first option needs reactants which will provide the impurity which introduces the middle gap level, while the second option involves a complicated process to get a very high purity material which is difficult to conclude successfully. Finally the option of growing epilayers slightly out of stoichiometry in order to introduce compensating defects which reduce the free charge carriers concentration, as it has been described before for bulk material, has not been achieved until now.
In our Mexican patent application No. 13192 entitled "PROCESS TO PREPARE GaAs EPITAXIAL LAYERS BY CLOSE SPACE VAPOR TRANSPORT," a process is characterized by placing the substrate material and source material very close and facing each other. The space between the substrate material and the source material is filled by a gas mixture, such as a transporting gas and H.sub.2. The substrate material and source material are heated simultaneously but at different temperatures from each other. The transporting gas reacts with both source and substrate materials, but because of the higher temperature of the source material, it produces a higher partial pressure of the products of the reaction than the partial pressure on the surface of the substrate. This difference in pressure gives rise to a gas diffusion of the products of the reaction from the source toward the substrate surface, which raises the pressure on the substrate surface above its equilibrium pressure. The higher pressure causes reverting the sense of this reaction and recovering the initial semiconductor but deposited on the substrate.
However, although the results obtained on GaAs epitaxialy grown with this technique were very interesting, other important parameters such as the growth rate effect on layer properties have not yet been studied.
An object of this invention is a process to grow semi-insulating epitaxial layers of the semiconductor materials of arsenides and phosphides without intentionally adding impurities to compensate the free charge carriers.
This invention relates to the fact that through the proper choice of temperature and growth rate of crystalline layers using any vapor phase epitaxy technique, it is possible to grow semi-insulating single crystalline layers of the semiconductor materials hereby mentioned in spite of the presence of residual impurities and without intentionally adding impurities to compensate for them. In any vapor phase technique, the growth rate needed to obtain a semi-insulating layer is a function of the growth temperature and the purity of the material usually grown with it. In our case, the semi-insulating nature of the epilayers grown is due to the presence of the same atoms which constitutes the crystal. For instance, Ga and As for the case of GaAs, but placed in such a way that they compensate the free charge carrier making the grown material semi-insulating.
The process is characterized by the following steps:
1) Preparation of a substrate for growing epitaxial layers of arsenides and phosphides of metals of the group III of the periodic table, free of any kind of contamination, organic or inorganic.
2) Introduction of the prepared substrate into the vapor phase reactor growth chamber, preferentially of the Close Space Vapor Transport (CSVT) type or any other of the vapor phase type.
3) Preparation of the growth chamber as a function of the type of reactor being used, for example molecular beam epitaxy, chemical vapor deposition using halogens, hydrides or metal-organic reactants, but preferentially of the CSVT type.
4) Growth of the epilayer using preferentially a CSVT type reactor, by heating simultaneously the source material, an arsenide or phosphide of metals of the group III of the periodic table, and the substrate materials at fixed but different temperatures between 450.degree. and 1150.degree. C.
It is therefore, an object of this invention to provide a process to grow semi-insulating single crystalline epitaxial layers which allows production of semi-insulating layers at high growth rates, which are useful for making electronic devices.
It is another object of this invention to provide a process to grow semiconductor epitaxial layers controlling the deep levels concentration in them.
It is still a further object of this invention to provide a process to grow semi-insulating epitaxial layers that does not need the use of toxic products or that gives off toxic byproducts.
It is a further object of this invention to provide a process to grown on ordinary single crystalline substrates semiconductor semi-insulating buffer epitaxial layers to be used for making integrated circuits and other electronic devices.